earticle

Clock Gating Based Energy Efficient and Thermal Aware Design of Latin Unicode Reader for Natural Language Processing on FPGA

Ritu Singh, Kartik Kalia, M H Minver, M Akbar Hussain

보안공학연구지원센터(IJUNESST) International Journal of u- and e- Service, Science and Technology Vol.9 No.8 2016.08 pp.75-86

Clock Gating Based Energy Efficient and Thermal Aware Design For Vedic Equation Solveron 28nm and 40nmFPGA SCOPUS

Bishwajeet Pandey, Sujeet Pandey, Shivani Sharma, Kartik Kalia, Khyati Nanda, M Akbar Hussain

보안공학연구지원센터(IJCA) International Journal of Control and Automation Vol.9 No.7 2016.07 pp.101-112

Design and Analysis of 4 Bit Johnson Counter Using Clock Gating

Sonia Sharma, Neeraj Kr. Shukla

보안공학연구지원센터(IJHIT) International Journal of Hybrid Information Technology Vol.9 No.8 2016.08 pp.359-366

Low Power Correlator Using Signal Range and Sub Word Based Clock Gating Scheme

A. Ranganayakulu, K. Satyaprasad

보안공학연구지원센터(IJHIT) International Journal of Hybrid Information Technology Vol.9 No.3 2016.03 pp.159-170

Power & Area Efficient Router in 2-D Mesh Network-on-Chip Using Low Power Methodology - Clock Gating Techniques

Sudhir N. Shelke, Pramod B. Patil

보안공학연구지원센터(IJHIT) International Journal of Hybrid Information Technology Vol.5 No.3 2012.07 pp.105-122

Clock Gated Multi Coding Technique for the Estimation of Transition Activities in Digital Circuits

R. Preyadharan, M. Siva Sankari, A.Tamilselvan, K. Rathinakumar, M. Nithiyaa

보안공학연구지원센터(IJHIT) International Journal of Hybrid Information Technology Vol.8 No.5 2015.05 pp.159-164

Clock-gating 을 고려한 저전력 8-bit 마이크로프로세서 설계에 관한 연구

전종식

[Kisti 연계] 한국전자통신학회 The Journal of the Korean institute of electronic communication sciences Vol.2 No.3 2007 pp.163-167

Design and FPGA Implementation of FBMC Transmitter by using Clock Gating Technique based QAM, Inverse FFT and Filter Bank for Low Power and High Speed Applications

Sivakumar, M., Omkumar, S.

[Kisti 연계] 대한전기학회 Journal of electrical engineering & technology Vol.13 No.6 2018 pp.2479-2484

Low-Power Systolic Array Viterbi Decoder Implementation With A Clock-gating Method

류제혁, 조준동

[Kisti 연계] 한국정보처리학회 정보처리학회논문지 A Vol.a12 No.1 2005 pp.1-6

10-Bit 200-MS/s Current-Steering DAC Using Data-Dependant Current-Cell Clock-Gating

Yang, Byung-Do, Seo, Bo-Seok

[Kisti 연계] 한국전자통신연구원 ETRI journal Vol.35 No.1 2013 pp.158-161

ODC 클럭 게이팅을 이용한 저전력 Interface 회로설계

양현미, 김희석

[Kisti 연계] 대한전자공학회 대한전자공학회 학술대회논문집 2008 pp.597-598

클록 게이팅을 이용한 저전력 UART 설계

오태영, 송승완, 김희석

[Kisti 연계] 대한전자공학회 대한전자공학회 학술대회논문집 2005 pp.865-868

클럭 게이팅 구동신호 기반 상위수준 전력모델의 전력 상태 수 감소

최호석, 이준환

[Kisti 연계] 대한전자공학회 Journal of the Institute of Electronics Engineers of Korea Vol.52 No.9 2015 pp.28-35

Clock-gating 방법을 사용한 저전력 시스톨릭 어레이 비터비 복호기 구현

류제혁, 조준동

[NRF 연계] 한국정보처리학회 KIPS Transactions on Computer and Communication Systems Vol.12 No.1 2005.02 pp.1-6