earticle

영어

VLSI designers are being motivated to explore the opportunities in low power design at different levels of abstraction in the fast growing mobile and battery power devices market. Research of the past few decades has been resulted in efficient electronic design automation tools which can be applied at several circuit and device level techniques to reduce power consumption. Research is being conducted to explore new techniques to utilize the application of specific signaling characteristics to reduce the power consumption. Few types of clock gating based power reduction techniques are established in present day EDA tools. The proposed research work presents novel sub word partitioned signal range based clock gating technique, which can be very efficient in signal processing applications. A scalable VHDL model is developed for the Correlator architecture with the proposed clock gating scheme. MATLAB script generated test data is used for functional verification. Xilinx FPGA based synthesis and power analysis tools are employed to analyze the power optimization of proposed architecture. The simulation results demonstrate power optimization without compromising on the performance. The results show power saving up to 31% for narrow band signal input conditions.