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Clock Gated Multi Coding Technique for the Estimation of Transition Activities in Digital Circuits

초록

영어

In this paper, estimation of transition activity in multi coding technique with the help of hamming code estimator is done and power consumption is reduced using clock gating technique. The VLSI technology allows thousands of transistors in a single chip. In order to integrate more functions in a single chip and to improve their performance, the feature size of the transistors are continue to shrink. This results in maximum power dissipation of the circuit followed by heat removal and cooling of the circuit. The charging and discharging of the internal node capacitance due to transition activity highly contributes to dynamic power dissipation. Mainly the power dissipation occurs due to the transition activity and this can be estimated using hamming code estimator. Coded data is given to the hamming code estimator from each coding type. Estimated code is compared with the help of comparator, this result in analysis of the minimum transition activity for the code in appropriate coding technique. Also clock gating is used to minimize the unnecessary power consumed in the idle state.

목차

Abstract
 I. Introduction
  1.1. Clock Gating
  1.2. Hamming Distance
  1.3. Some Coding Techniques
 2. Proposed Work
 3. Methodology
 4. Simulation Results
 5. Conclusion
 6. Future Work
 References

저자정보

  • R. Preyadharan PG Scholar, Department of ECE, Knowledge Institute of Technology, Salem
  • M. Siva Sankari PG Scholar, Department of ECE, Knowledge Institute of Technology, Salem
  • A.Tamilselvan Assistant Professor, Department of ECE, Knowledge Institute of Technology, Salem
  • K. Rathinakumar Assistant Professor, Department of ECE, Knowledge Institute of Technology, Salem
  • M. Nithiyaa Assistant Professor, Department of ECE, Knowledge Institute of Technology, Salem

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