원문정보
초록
영어
In this paper, we are integrating clock gating in design of energy efficient equation solver circuits based on Vedic mathematics. Clock gating is one of the best energy efficient techniques. The Sutra 'SunyamSamyasamuccaye' says thatif sum of numerator and sum of denominator is same then we can equate that sum to zero and find the value of unknown variable. In order to test the portability of our design, we are operating our design with respective frequency of different mobile architecture. Operating frequency of iPhone6 is 2100MHz. For thermal analysis of our energy efficient design, we have taken temperatures of four different regions of Furnace Creek Ranch (329.85K), Mohenjo-Daro (326.65K), and median temperature of Delhi (313.15K) and standard normal temperature (294.15K). Saving in clock power dissipation is 96.15% for 1400MHz, 94.59% for 1.2GHz, 93.75% for 2100MHz, 94.23% for 1700MHz, 94.54% for 1800MHz, and 94.02% for 2.2GHz, when we use gated clock instead of un gated one on 40nm FPGA and temperature is 329.85K. Power consumption in 28nm FPGA is less than 40nm FPGA.
목차
1. Introduction
2. Power Analysis
2.1. Power Analysis at 329.85 Kelvin Ambient Temperature
2.2. Power Analysis at 326.65K Ambient Temperature
2.3. Power Analysis at 313.15K Ambient Temperature
2.4. Power Analysis at 294.15KAmbient Temperature
2.5. Power Analysis ForDifferent Frequencies andDifferent Temperature on 28nm FPGA
2.6. Power Analysis For Different Frequencies & Different Temperature on 40nm FPGA
2.7. Comparison between Kintex-7 and Virtex-6 FPGA
3. Conclusion
4. Future Scope
References