원문정보
초록
영어
To overcome limitations of binary computing systems, such as interconnect delays and power inefficiency, we demonstrate CMOS-compatible ternary logic devices based on TeOx/IGTO p-n heterojunction TFTs. Fabricated at 150 °C, these devices exhibit stable negative differential transconductance (NDT) with a peak-to-valley ratio over 103. By monolithically integrating them with p-channel TeOx TFTs, we realize ternary inverters capable of producing a distinct intermediate logic state through optimized transconductance alignment. This lowtemperature process supports scalable, energy-efficient logic integration, highlighting oxide semiconductors as a strong platform for next generation multi-valued computing.
목차
1. Introduction
2. Experimental Procedure
3. Results and Discussion
4. Conclusion
References
