earticle

영어

This paper presents an efficient summation circuit optimized for high-performance computational applications. The proposed design enables the addition of five 8-bit numbers using modular components, including add_10to4 modules and a 6-bit carry lookahead adder. The proposed circuit achieves a significant reduction in propagation delay enabling GHz-level one cycle operation. Compared to conventional ripple carry adders and carry lookahead adders, the proposed design demonstrates about 11 times speedup while maintaining a acceptable transistor overhead, contributing only 3–4% of modern processor resources. The circuit was validated through simulation in Logisim Evolution, confirming its accuracy and efficiency. Furthermore, the proposed summation circuit was successfully applied in matrix multiplication, demonstrating its potential for broader numerical computation tasks. This work provides a promising approach for integrating optimized arithmetic units into System-on-Chip (SoC) architectures, significantly enhancing computational efficiency.