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Poster Session IV

High-Throughput Multi-Threaded Non-binary LDPC Decoder Architecture

원문정보

Thang Xuan Pham, Tuy Nguyen Tan, Phap Duong-Ngoc, Huyen Pham Thi, Hanho Lee

한국차세대컴퓨팅학회 한국차세대컴퓨팅학회 학술대회 The 7th International Conference on Next Generation Computing 2021 2021.11 pp.374-376
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초록

영어

This paper introduces an efficient non-binary low-density parity-check (NB-LDPC) decoder architecture, in terms of increasing decoding throughput. By taking advantages of non-binary quasi-cyclic LDPC codes, a new layered decoding algorithm and corresponding efficient hardware architecture are introduced. The proposed method can improve parallelism in decoding estimations of NB-LDPC decoder while remaining error-correcting performance. The implementations results confirmed that the proposed decoder with two threads can achieve a throughput of about 2.78 Gbps, which is around 1.63 times faster than that of the state-of-the-art decoder at almost the same hardware efficiency.

목차

Abstract
I. INTRODUCTION
II. NB-LDPC LAYERED DECODING ALGORITHM
III. PROPOSED MULTI-THREADED NB-LDPC DECODER
A. Multi-threaded NB-LDPC algorithm
B. Proposed two-threaded NB-LDPC decoder architecture
IV. IMPLEMENTATION RESULTS IN COMPARISONS WITH THE PREVIOUS WORKS
V. CONCLUSIONS
ACKNOWLEDGMENT
REFERENCES

키워드

저자정보

  • Thang Xuan Pham Dept. of Information and Communication Engineering Inha University
  • Tuy Nguyen Tan Dept. of Information and Communication Engineering Inha University
  • Phap Duong-Ngoc Dept. of Information and Communication Engineering Inha University
  • Huyen Pham Thi Dept. of National Laboratory of Information Security Hanoi, Vietnam
  • Hanho Lee Dept. of Information and Communication Engineering Inha University

참고문헌

자료제공 : 네이버학술정보

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