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Poster Session Ⅰ: ICT-Future Vehicle

High-Speed Memory Interface for High-Performance Computing System

원문정보

Taehwan Kim, Donghyun Kim, Hyunmin Shin, Saransh Rajjarwal, Gyungsu Byun

한국차세대컴퓨팅학회 한국차세대컴퓨팅학회 학술대회 The 8th International Conference on Next Generation Computing 2022 2022.10 pp.207-209
피인용수 : 0건 (자료제공 : 네이버학술정보)

초록

영어

A 4Gb/s transceiver with the CTLE is presented. The proposed CTLE can recover the attenuated data up to 7dB by changing the digital codes which are received from the digital control logic. The proposed transceiver was designed and fabricated in 180-nm CMOS technology and consumes 60.37mW.

목차

Abstract
I. INTRODUCTION
II. TRANSCEIVER DESIGN
A. Transmitter (TX) Design
B. Receiver (RX) Design with CTLE
C. Digital Logic for Digital Calibration
IV. CONCLUSION
REFERENCES

키워드

저자정보

  • Taehwan Kim Information and Communication Engineering Inha University
  • Donghyun Kim Information and Communication Engineering Inha University
  • Hyunmin Shin Information and Communication Engineering Inha University
  • Saransh Rajjarwal Information and Communication Engineering Inha University
  • Gyungsu Byun Information and Communication Engineering Inha University

참고문헌

자료제공 : 네이버학술정보

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