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논문검색

반도체 제조라인 레이아웃 평가를 위한 실용적인 Lot 이동거리 계산방법

원문정보

A Practical Estimation Method for the Lot Travel Distance for Evaluating Semiconductor Fabrication Layouts

서민석, 임대은

피인용수 : 0(자료제공 : 네이버학술정보)

초록

영어

In this paper, a practical estimation method is developed for the lot travel distance in order to evaluate semiconductor unified fabrication layouts using the absorbing Markov chain. The lot travel distance is defined as the total distance that a lot travels from the first process to the last process; it can be used to investigate whether a fabrication layout design is reasonable. Furthermore, unified fabrication has not yet been introduced in the literature; it is a fabrication method that uses only one type of automated material handling system (AMHS). When designing semiconductor fabrication layouts, every aspect of all alternatives should be investigated meticulously. The widely known and accepted methods, such as sophisticated simulations and mathematical modeling with high accuracy, require an extensive time period to build the model. However, in the early stages of the layout design, simple and insightful methods are required in order to investigate the numerous alternatives during a short time period. This paper presents a simple estimation method for the travel distance of a lot during its lifetime in a fabrication.

목차

Ⅰ. 서론
 Ⅱ. 기존 문헌 연구
 Ⅲ. 연구 대상 소개 및 가정
 Ⅳ. 수리모형
 Ⅴ. 결론
 참고문헌
 Abstract

저자정보

  • 서민석 Min-Seok Seo. 삼성전자 반도체 사업부 책임
  • 임대은 Dae-Eun Lim. 백석대학교 경상학부 조교수

참고문헌

자료제공 : 네이버학술정보

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