earticle

영어

The multiplier occupies more area in the design of FIR filter, which is the basic element of any filter. The low complexity and power architecture of pulse shaping FIR filter for multi standard digital up converter was designed. In the existing system, a 2-bit binary common sub expression (BCS) elimination algorithm and shift and add method are used to design an efficient multiplier in the pulse shaping filter. In this paper, two different types of adders are used in accumulation unit of the filter to reduce power consumption and delay compared to the existing system. Adders plays vital role in Digital signal processing applications and also used in the digital integrated circuits. With the advances in technology, several researchers have contributed towards designing adders with either high speed, less power consumption, low area or the combination of them. In this Paper, we describes the analysis of speed, power and delay of two different types of adders like carry select adder and carry save adder for accumulation unit of root raised cosine (RRC) filter. The number of additions are reduced by using these adders and succeeded in reducing the delay, power and area. The designed pulse shaping FIR interpolation filter is simulated and synthesized using Xilinx tool for Spartan 3E family devices and simulation results are presented.