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In this work, energy efficient ROM is being designed using Kintex 7 which is able to scale down the circuit to 28 nm. For Testing the ROM compatibility, ROM is operated on operating frequencies (10GHz, 15GHz, 20GHz, 25GHz ) .Whenever capacitance is scaled down from 15pf to 5pf, there is I/O power and total power reduction but it is observed that there is no reduction in Clock power, and a very small reduction in leakage power. FPGA is an Integrated Circuit that comprises of input/output buffer, programmable interconnect structure and an array of configurable logic blocks, which featurisms fast prototyping and consumer configurability which gives the advantage of short turnaround time( i.e. time required from start of process till a functional chip is obtained).10MBits of on chip Memory is being provided on Xilinx FPGA in 36Kbits blocks, which supports dual port operation. Stub Series Terminated Logic (SSTL) is an Input/output standard which is selected because it avoids the transmission lie reflection and overall power dissipation. The purpose of Voltage scaling is to reduce leakage power. When capacitance of output load is scaled from 50pF to 5pF, there are 32-37% saving in I/O Power, 0-0.1% Leakage Power saving, there will be a 1-5% saving in Total Power. This design is implemented on Kintex-7 FPGA using Xilinx ISE & Verilog. The technique of Frequency Scaling has been used to reduce the leakage power consumption within the range of 80% to 44.8%, consumption in total power in range of 45.8% to 21.36% and the reduction in Junction temperature range is from 3.5% to 1.6% for 10GHz frequency.