earticle

영어

Phase frequency detector is the main component that is used in almost all high speed communication system especially in sensors. With the improving technology it is important for phase frequency detector to meet the requirement of modern communication system. Such requirements can be improved delay and less power consumption. With this idea this paper presents the Phase Frequency Detector having less power consumption and minimal delay. Conventional latch based phase frequency detectors are most commonly used, therefore we propose an enhanced phase frequency detector which can meet the requirement of modern circuits and will reduce the shortcomings of conventional circuit. In this paper standard D flip flop is simulated and then a comparison is made between conventional and proposed model .The proposed model uses two extra transistors to reduce the blind zone, dead zone which ensures improved device characteristics. Simulations are done using tanner v14.11 tools with .35 μm CMOS technology.