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High Performance Energy Efficient Different Counters Design and Implementation on 28nm FPGA

초록

영어

In this paper, we have done analysis of ten different counters in term of frequency related to high performance and power dissipation related to energy efficiency. Conserving energy is now a days a very important aspect. In order to conserve energy consumption of our design, we are using dynamic frequency scaling with default LVCMOS18 IO Standard technique which plays a very important role in power saving. Our design is capable to operate with 1 THz frequency that deliver high performance in less time i.e. 1 pico second. Among 10 different counters, 8 bit simple up counter provide maximum reduction in total power that is 84.25% and 98.33% between a frequency range of 1GHz to 10GHz and 1 GHz to 100 GHz respectively.

목차

Abstract
 1. Introduction
 2. Schematics of Different Counters
  A. 8-bit Simple up Counter
  B. Up Counter with Load
  C. Up Down Counter
  D. LFSR
  E. LFSR Up Down
  F. Gray Counter
  G. One Hot Counter
  H. Divide By 2 Counter
  I. Divide By 3 Counter
  J. Divide By 4.5 Counter
 2. Related Work
 3. Results
  A. 8-bit Simple Up Counter
  B. Up Counter with Load
  C. Up Down Counter
  D. LFSR
  E. LFSR Up Down
  F. Gray Counter
  G. One Hot Counter
  H. Divide By 2 Counter
  I. Divide By 3 Counter
  J. Divide by 4.5 Counter
 4. Conclusion
 5. Future Scope
 References

저자정보

  • Daizy Gupta Department of Electronics and Communication Chitkara University Chandigarh, India
  • Devanshi Mahajan Department of Electronics and Communication Chitkara University Chandigarh, India
  • Bishwajeet Pandey Department of Electronics and Communication Chitkara University Chandigarh, India
  • Amanpreet Kaur Department of Electronics and Communication Chitkara University Chandigarh, India
  • Amit Yadav Department of Electronics and Communication Chitkara University Chandigarh, India
  • Apoorv Verma Department of Electronics and Communication Chitkara University Chandigarh, India

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