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영어

In this work, we report a detailed analysis on a low power memory circuit using buffer, extraction and style based RAM design on 28nm Field Programmable Gate Array (FPGA).The designing of this memory circuit is done by Verilog as HDL, Xilinx ISE 14.6 simulator with kintex-7 FPGA. Different RAM styles and RAM extracts are compared on basis of power consumption and reduction. Auto RAM style is the default RAM style and it consumes minimum power as compared to block RAM. The RTL schematic shows I/O ports, nets and primitives. Bufgdll also consumes less power and power reduction is also maximum for bufdll and auto RAM as compared to block RAM, ibufg and RAM extract yes. Auto RAM at 10GHz frequency can be used in designing various applications like in radio astronomy, microwave devices and communications, wireless LAN, most modem radars, communications satellites, satellite television broadcasting.