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Design of Low Power and Secure Implementation of SBox and Inverse-SBox for AES

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In the cutting edge world, data security has turned into an essential issue furthermore the innovation is going to increment quickly. In this paper, the symmetric key standard for encryption and decoding is propelled Encryption standard (AES). The key stride in the AES is the "S-Box". S Box is an imperative segment for symmetric key calculations. An S-box takes some number of information bits "p" and interprets them in yield bits 'q', where "p" is not as a matter of course equivalent to 'q'. In AES Encryption calculation Sub Bytes change uses S-Box and Inverse S-Box uses Inverse of S-Box. The Sub Bytes substitution is a nonlinear byte substitution that uses substitution table (i.e., S-Box) takes the multiplicative reverse (GF (28)) and infers a relative change to do the Sub Bytes change. Though, converse Sub Bytes Substitution additionally uses gaze upward table (i.e., Reverse S-Box) takes an opposite relative change and after that suggests multiplicative backwards of Galois Field (GF (28)). In this printed material, we investigated substitution table/reverse substitution table, multiplicative opposite and relative change and its converse (i.e. reverse relative change) science in Galois field. A standout amongst the most basic issues in AES is the force utilization. Here, we predominantly centered around the force utilization and in addition security of S-box which is the most power devouring square in the AES. We have executed and reproduced S-Box and Inverse S-Box Lookup table and acquired another improved scrambled Lookup table for more upgraded mystery by utilizing Xilinx Spartan-3 assessment board. The Simulation and execution instruments utilized are Xilinx ISE 14.1i and ModelSim 6.0.

목차

Abstract
 1. Introduction
 2. The AES Algorithm
 3. Encryption and Decryption
 4. S-Box and Inverse S-Box Architecture
 5. RTL View and Simulation Results of S-Box and Inverse S-Box
  5.1. Results and RTL View of S-BOX and Inverse S-BOX
  5.2. Simulation Results
  5.3.2. Synthesis Table
 6. Encryption with Secrecy Enhancement
 7. Power Analysis of S-BOX and Inverse S-BOX with and without Clock Gating
 8. Conclusion
 References

저자정보

  • Divya Sharma Department of Electronics & Communication, JIIT-Noida (U.P.)-India
  • Ankur Bhardwaj Department of Electronics & Communication, JIIT-Noida (U.P.)-India
  • Harshita Prasad Department of Electronics & Communication, UTU-Dehradun (U.K.)-India.
  • Jyoti Kandpal Department of Electronics & Communication, UTU-Dehradun (U.K.)-India.
  • Abhay Saxena Department of Computer Science, DSVV-Haridwar (U.K.)-India.
  • Kumar Shashi Kant Department of Electronics & Communication, SIT-Pune-India.
  • Gaurav Verma Department of Electronics & Communication, JIIT-Noida (U.P.)-India

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