earticle

영어

This paper describes a capacitor-less high PSRR low-dropout (LDO) linear regulator with transition enhancement technique. The proposed LDO uses a 2-stage error amplifier for high PSRR. To maintain high stability without a big external capacitor, cascode compensation technique and current buffer compensation technique are adopted with the small internal capacitance of 1.15pF for local compensation, while the nested Miller compensation technique is used for global compensation. Also, an additional voltage-spike detection circuit improves the load transient response. The LDO operates with an input voltage of 3.3V and provides the output voltage of 1.8V. Simulated line and load regulation are 0.26mV/V and 1.8uV/mA, respectively. The power supply rejection ratio (PSRR) is -90dB and –30dB at DC and 1MHz, respectively. The chip area is 240μm x 110μm.