원문정보
보안공학연구지원센터(IJSEIA)
International Journal of Software Engineering and Its Applications
Vol.10 No.6
2016.06
pp.81-92
피인용수 : 0건 (자료제공 : 네이버학술정보)
초록
영어
In this particular work, we have done power analysis of DES algorithm implemented on 28nm FPGA using HTML (H-HSUL, T-TTL, M-MOBILE_DDR, L-LVCMOS) technology. In this research, we have used high performance software Xilinx ISE where we have selected four different IO Standards i.e. MOBILE_DDR, HSUL_12, LVTTL and LVCMOS (LVCMOS_15, LVCMOS_18, LVCMOS_25 and LVCMOS_33). We have done power analysis of on-chip power like clock power, signals power, IO power, leakage power and supply power. We notified our analysis at five different voltages like 0.5V, 0.8V, 1.0V, 1.2V and 1.5V.
목차
Abstract
1. Introduction
2. Related Work
3. Power Analysis
4. Power analysis using MOBILE_DDR as IO standard
5. Power Analysis using HSUL_12 as IO Standard
6. Power Analysis using LVTTL as IO Standard
7. Power Analysis using LVCMOS as IO Standard
8. Total Power and Supply Power Variation at Various Voltages Level
9. Conclusion
10. Future Scope
References
1. Introduction
2. Related Work
3. Power Analysis
4. Power analysis using MOBILE_DDR as IO standard
5. Power Analysis using HSUL_12 as IO Standard
6. Power Analysis using LVTTL as IO Standard
7. Power Analysis using LVCMOS as IO Standard
8. Total Power and Supply Power Variation at Various Voltages Level
9. Conclusion
10. Future Scope
References
저자정보
참고문헌
자료제공 : 네이버학술정보