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논문검색

Design OF FPEZ-Source Network with Reduced Switches FED Induction Motor

원문정보

초록

영어

This Project deals with an fully parallel Embedded Z-source inverter(FPEZ) to control the three phase induction motor. Z-Source inverter is a single-stage converter which performs both buck-boost energy conversions using the LC impedance network. The further advancement in the Z-Source inverter is the partially parallel Embedded Z-Source(PPEZS) inverter that can produce same gain as Z-Source inverter but with lower capacitor voltage and ripples . In order to overcome the drawbacks of PPEZS, Fully parallel EZ-(FPEZS) Source inverter is proposed. The proposed inverters provide a high boost voltage inversion ability, a lower voltage stress across the active switching devices and capacitors with a continuous input current. In addition, they can suppress the startup inrush current, which otherwise might destroy the devices. The proposed system reduces six switch three phase inverter to four switch three phase inverter. This makes system compact which reduces cost and switching losses, line harmonics, improves power factor, reliability and extends the output voltage range. The system is modeled using Proteus and Simulink simulation. This paper presents the operating principles, analysis, and simulation results of FPEZ Source inverter.

목차

Abstract
 I. Introduction
  1.1 Voltage Source Inverter (VSI)
  1.2 Current Source Inverter (CSI)
 II. Impedance Source
  2.1. Impedance Source Network
  2.2. Equivalent Circuit &Modes Of Operation:
 III. Embedded Z Source Inverter
  3.2. Fully Parallel EZ Source (FPEZ)
 IV. Implementation OF FPEZ FED Induction Motor
  4.1. System Overview
  4.2. Control Circuit
 V. Design OF FPEZ with Reduced Switches FED IM Motor
 VI. Simulation of Hardware Results
 VII. Conclusion
 References

저자정보

  • V. Vidhya P.G Scholar Sriram Engineering College, Perumalpattu
  • L.Parimala Assistant Professor Sriram Engineering College, Perumalpattu

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