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논문검색

Low Power Gated-Clock Design for Multi-core DSP Based SDR Platform

원문정보

Xu Li, An Peng, Wang Yu, Li Jun

보안공학연구지원센터(IJUNESST) International Journal of u- and e- Service, Science and Technology Vol.9 No.6 2016.06 pp.169-178
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초록

영어

With the rapid development of wireless communication systems, multi-core DSP with high computing performance is an important part of SDR (Software-Defined Radio) platform. Research has focused on low-power design in SDR platform since the SDR platform is sensitive to power consumption. Following the baseband digital signal processing features of SDR application, this paper proposes a data-driven and task-driven gated-clock architecture. The DSP cores in the multi-core DSP can be turned on and turned off with this architecture at the appropriate time. Experiments show that the proposed low power gated-clock architecture can provide effective low-power performance for multi-core DSP in SDR platforms.

목차

Abstract
 1. Introduction
 2. Related Work
 3. Multi-core DSP Low-Power Design
  3.1. Data Driven Gated-clock
  3.2. Task Driven Gated-clock
  3.3. Dynamic Turn Off and Static Turn On
 4. Evaluation and Analysis
 5. Conclusions
 Acknowledgments
 References

키워드

저자정보

  • Xu Li School of Electronic and Information Engineering, Ningbo University of Technology, Ningbo 315016, China
  • An Peng School of Electronic and Information Engineering, Ningbo University of Technology, Ningbo 315016, China
  • Wang Yu School of Electronic and Information Engineering, Ningbo University of Technology, Ningbo 315016, China
  • Li Jun School of Electronic and Information Engineering, Ningbo University of Technology, Ningbo 315016, China

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