원문정보
보안공학연구지원센터(IJHIT)
International Journal of Hybrid Information Technology
Vol.9 No.5
2016.05
pp.285-292
피인용수 : 0건 (자료제공 : 네이버학술정보)
초록
영어
In Combination logic there are some patterns which commonly occur and it is convenient to represent these in their own separate units often they are also available as separate integrated circuits. This research paper covers the two of these, the decoder and the multiplexer. In this work, designing of 2:1 MUX and MUX Based Decoder using SCL (Source Coupled Logic) is done. Power and value of current spike (Rail–to-Rail current) is found for the circuits. The Simulation is done using 180nm technology using TANNER (Version 9.2) tool.
목차
Abstract
1. Introduction
2. Decoder Circuit
3. Multiplexer Circuit
4. Source Coupled Logic (SCL)
5. Experimental Results and Proposed Methodology
5.1. Multiplexer-Minimization (MUX-MIN) Method
5.2. 2:1 MUX using SCL
5.3. Mux Based Decoder Using Scl
6. Conclusion
References
1. Introduction
2. Decoder Circuit
3. Multiplexer Circuit
4. Source Coupled Logic (SCL)
5. Experimental Results and Proposed Methodology
5.1. Multiplexer-Minimization (MUX-MIN) Method
5.2. 2:1 MUX using SCL
5.3. Mux Based Decoder Using Scl
6. Conclusion
References
저자정보
참고문헌
자료제공 : 네이버학술정보