earticle

영어

Design a delay free FPGA-based Proportional-Integral-Derivative (PID) controller to control of first order delay system is the main objective in this research. In order to provide high performance micro-based controller, FPGA-based PID controller based on design Derivative and Integral algorithm is selected. Conventional PID controller is a stable linear type model-free controller that reduces the delay time in first order delay system. This controller has acceptable performance in presence of uncertainty (e.g., overshoot=0%, rise time=0.8 second, steady state error = 1e-9 and RMS error=1.8e-12). In this research, linear controller need real time mobility operation, and one of the most important devices which can be used to solve this challenge is Field Programmable Gate Array (FPGA). FPGA can be used to design a controller in a single chip Integrated Circuit (IC). In HDL based derivative algorithm the minimum input arrival time before clock is 16.466 ns and the maximum frequency is 60.73 MHz, but in the best design action, the maximum frequency to design this single chip algorithm should be 63.629 MHz. In HDL integral algorithm the minimum input arrival time before clock is 15.599 ns and the maximum frequency is 64.1 MHz, but in the best design action, the maximum frequency to design this single chip algorithm should be 178.190 MHz.