SSTL IO Standard Based Low Power Arithmetic Design Using Calana Kalanabhyam On FPGA

Gaurav Verma; Sushant Shekhar; Kumar Shashi Kant; Vikas Verma; Himanshu Verma; Bishwajeet Pandey

SSTL IO Standard Based Low Power Arithmetic Design Using Calana Kalanabhyam On FPGA

원문정보

Gaurav Verma, Sushant Shekhar, Kumar Shashi Kant, Vikas Verma, Himanshu Verma, Bishwajeet Pandey

보안공학연구지원센터(IJCA) International Journal of Control and Automation Vol.9 No.4 2016.04 pp.271-278 SCOPUS

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초록

영어

Vedic mathematics consists of 16 formulas. Calanakalanabhyam is a Sanskrit word meaning “Sequential motion”. Using this Vedic technique, we will find the roots of the equation in few seconds. We have tried to make an energy efficient Calanakalanabhyam Vedic formula based root finder with 4 inputs and 2 outputs. We have taken different SSTL Input/Output Standards and have done Study of Power by varying frequencies. SSTL Input/Output Standards used in this paper are SSTL15, SSTL18_II, SSTL135, SSTL12, SSTL18_I. The code has been implemented on 28nm FPGA platform, XC7K160T device, FBG676 package and -3 speed grade. With our proposed technique, we have 41-60% achieved reduction in total consumption of power with frequency scaling.

키워드

저자정보

Gaurav Verma Jaypee Institute of Information Technology Noida, India,
Sushant Shekhar Jaypee Institute of Information Technology Noida, India,
Kumar Shashi Kant Symbiosis Institute of Technology, India
Vikas Verma Indian Institute of Technology, Roorkee
Himanshu Verma Jaypee Institute of Information Technology Noida, India
Bishwajeet Pandey Gyancity Research Lab, India

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