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논문검색

SSTL Input/Output Standard Based Energy Efficient Multiplier Design Using Urdhva Tiryagbhyam on 28nm FPGA

초록

영어

We have taken different set of frequencies and done study of power by varying frequencies and with different SSTL Standard Used for Input/Outputs at fixed temperature i.e. 25 degree Celsius. SSTL family includes SSTL15, SSTL18_II, SSTL135, SSTL12, SSTL18_I. Power has been calculated on these standards and analysis has been done to find the standard with least power consumption and to make an energy efficient device. The proposed multiplication algorithm is coded in Verilog, synthesized and simulated using Xilinx ISE design suit 14.2.at the end we can conclude that there can be 34-50% power consumption reduced by using frequency scaling technique and using SSTL Standard used for Input/Output. The maximum power has been consumed by SSTL18_II and minimum power consumption is by SSTL12.

목차

Abstract
 1. Introduction
 2. Power Analysis
  A. Study of power for SSTL15 STANDARD USED FOR INPUT/OUTPUT
  B. Study of power for SSTL18_II standard used for input/output
  C. Study of power for SSTL135 standard used for input/output
  D. Study of power for SSTL12 standard used for input/output
  E. Study of Power for SSTL18_I Standard Used for Input/Output
  F. Study of power for different standard used for input/OUTPUT with Various frequencies
 3. Conclusion
 4. Future Scope
 References

저자정보

  • Md. Saifur Rahman Noakhali Science and Technology University, Bangladesh
  • Md Mahbub E Noor Department of CSE, University of Barisal, Bangladesh
  • Tania Islam Department of CSE, University of Barisal, Bangladesh
  • Rohit Tiwari National Institute of Technology, Srinagar, India
  • Kartik Kalia Gyancity Research Lab, India
  • Tanesh Kumar University of Oulu, Finland

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