원문정보
보안공학연구지원센터(IJHIT)
International Journal of Hybrid Information Technology
Vol.8 No.11
2015.11
pp.181-188
피인용수 : 0건 (자료제공 : 네이버학술정보)
초록
영어
Multiplier is the major component for processing of large amount of data in DSP applications. Using different recoding schemes in Fused Add-Multiply (FAM) design for the reduction of power and look up tables. The performances of 8-bit, 12-bit & 16-bit signed multipliers were designed and obtained results are tabulated using Efficient Modified Booth Recoding (EMBR) techniques, which can be used for low power applications.
목차
Abstract
1. Introduction
2. Motivation
3. Modified Booth Multiplier
3.1. Algorithm
4. Recoding Techniques of Sum to Efficient Modified Booth (S-MB)
4.1. Arithmetic of Structured Signed
4.2. Techniques of S-MB Recoding
6. Results
6.1. Results of 8-bit Signed Multiplier
6.2. Results of 12-bit Signed Multiplier
6.3. Results of 16-bit Signed Multiplier
7. Conclusion
References
1. Introduction
2. Motivation
3. Modified Booth Multiplier
3.1. Algorithm
4. Recoding Techniques of Sum to Efficient Modified Booth (S-MB)
4.1. Arithmetic of Structured Signed
4.2. Techniques of S-MB Recoding
6. Results
6.1. Results of 8-bit Signed Multiplier
6.2. Results of 12-bit Signed Multiplier
6.3. Results of 16-bit Signed Multiplier
7. Conclusion
References
저자정보
참고문헌
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