원문정보
보안공학연구지원센터(IJHIT)
International Journal of Hybrid Information Technology
Vol.8 No.10
2015.10
pp.7-14
피인용수 : 0건 (자료제공 : 네이버학술정보)
초록
영어
Multiplier is the major component for processing of large amount of data in DSP applications. Using different recoding schemes in Fused Add-Multiply (FAM) design for the reduction of power and look up tables. The performance of 16-bit signed and unsigned multipliers were designed and obtained results are tabulated using Efficient Modified Booth Recoding (EMBR) techniques, which can be used for low power applications.
목차
Abstract
1. Introduction
2. Motivation
3. Modified Booth Multiplier
3.1. Algorithm
4. Summation to Efficient Modified Booth Recoding Technique (S-MB)
4.1. Structured Signed Arithmetic
4.2. S-MB Recoding Techniques
5. Fused Add Multiply Implementation
6. Results
6.1 Results of 16-bit Signed Multiplier
6.2 Results of 16-bit Unsigned Multiplier
7. Conclusion
References
1. Introduction
2. Motivation
3. Modified Booth Multiplier
3.1. Algorithm
4. Summation to Efficient Modified Booth Recoding Technique (S-MB)
4.1. Structured Signed Arithmetic
4.2. S-MB Recoding Techniques
5. Fused Add Multiply Implementation
6. Results
6.1 Results of 16-bit Signed Multiplier
6.2 Results of 16-bit Unsigned Multiplier
7. Conclusion
References
키워드
저자정보
참고문헌
자료제공 : 네이버학술정보