원문정보
보안공학연구지원센터(IJSIA)
International Journal of Security and Its Applications
Vol.9 No.10
2015.10
pp.21-30
피인용수 : 0건 (자료제공 : 네이버학술정보)
초록
영어
Low Density Parity Check codes are FEC codes and consequently data rate is more. They are linear error correcting codes for transmitting a message over a noisy transmission channel. LDPC codes are finding increasing use in applications requiring reliable and highly efficient information transfer over noisy channels. These codes are capable of performing near to Shannon limit performance, Low Decoding Complexity. The main advantage of the parity check matrix is the decoder can correct all single-bit errors. In this Paper LDPC encoder and decoder architecture for coding 3-bit message vector will be analyzed and also designed using VHDL.
목차
Abstract
1. Introduction
2. System Design
2.1. LDPC Algorithm
2.2. Design of LDPC Architecture using VHDL Coding
3. Encoder Design
4. Channel Design
5. Decoder Design
5.1. Simulation Results
5.2. Applications of LDPC
6. Conclusion
References
1. Introduction
2. System Design
2.1. LDPC Algorithm
2.2. Design of LDPC Architecture using VHDL Coding
3. Encoder Design
4. Channel Design
5. Decoder Design
5.1. Simulation Results
5.2. Applications of LDPC
6. Conclusion
References
저자정보
참고문헌
자료제공 : 네이버학술정보