원문정보
보안공학연구지원센터(IJUNESST)
International Journal of u- and e- Service, Science and Technology
Vol.8 No.9
2015.09
pp.117-126
피인용수 : 0건 (자료제공 : 네이버학술정보)
초록
영어
In this paper a low-power pulse-triggered structure and a modified true single latch structure based on a signal feed-through scheme is designed in TSMC CMOS 180 nm technology. The Pulse triggered flip-flop (P-FF) solves the problem of long discharging path and achieves better speed and power performance. The pre and post lay-out simulations has been done using Cadence tool, the performance analysis on power-delay-product metrics are obtained through simulation and finally a 4-bit RAM is designed by using P-FF and then the implementation has been done on SOC 11.10 technology.
목차
Abstract
1. Introduction
2. P-FF Design based on Signal Feed through Scheme
3. Design of 4 Bit Static-RAM using P-FF
4. Implementation of 4 Bit Static-RAM using P-FF on SoC (System on Chip)
5. Simulation Results
6. Conclusion
References
1. Introduction
2. P-FF Design based on Signal Feed through Scheme
3. Design of 4 Bit Static-RAM using P-FF
4. Implementation of 4 Bit Static-RAM using P-FF on SoC (System on Chip)
5. Simulation Results
6. Conclusion
References
저자정보
참고문헌
자료제공 : 네이버학술정보