원문정보
초록
영어
Motion estimation (ME) and motion compensation (MC) are the key elements for frame rate up-conversion (FRUC) system. Fast and accurate motion estimation is the premise of high quality motion compensation. Unlike conventional unidirectional motion estimation which brings holes, overlaps and blocking artifacts, the bi-directional motion estimation does not produce any overlapped pixel or hole in the interpolated frames. As a result, the bi-directional motion estimation has better performance than conventional unidirectional motion estimation. This paper presents an efficient FPGA architecture targeting bi-directional motion estimation hardware implementation. This proposed architecture can achieve real-time processing for 1280x720@60Hz under 200MHz operating frequency. The design is described in Verilog HDL, verified in Virtex5 FPGA platform. Experimental results show that the proposed architecture has high performance and low cost for bi-directional motion estimation algorithm. This architecture can be used for video post-processing system.
목차
1. Introduction
2. Principle of Bi-directional Motion Estimation
2.1. Bi-directional Motion Estimation
2.2. Local Full Search Algorithm
2.3. Matching Criterion
3. Improved FPGA Architecture
3.1. Data Multiplex
3.2. FPGA Architecture
4. Synthesis Results and Experimental Results
4.1. Synthesis Results
4.2. Experimental Results
5. Conclusion
Acknowledgment
References