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논문검색

Timing-reliable Design of High-speed TigerSHARC 201 Link Transceiver

원문정보

Peng Wang, Ke Gong, You-chao Tu, Xiao-li Zhang, Xin-wu Chen

보안공학연구지원센터(IJSIA) International Journal of Security and Its Applications Vol.9 No.8 2015.08 pp.417-426
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초록

영어

TigerSHARC 201 link interface is a very efficient double data rate protocol. However, its inconsecutive characteristic of clock adds great difficulty for FPGA implementation when transmission rate is too high. In this paper, with specially-designed clock tree, ingenious rate decreasing strategy, plus proper control on FPGA place & routing processing, 8 group link transceivers with data rate over 500MB/s per lane were designed successfully on Xilinx Virtex6 XC6VLX130. Besides, no sophistic IOSERDES component was utilized. Whole design was completed via Verilog RTL code and Xilinx user constrained file. Presented design also has experienced harsh environment test, proved its efficiency and reliability.

목차

Abstract
 1. Introduction
 2. TS201 Link Protocol
 3. Link Transmitter Design
 4. Link Receiver Design
 5. Implementation Results
 6. Conclusion
 Acknowledgments
 References

키워드

저자정보

  • Peng Wang College of Physics & Electronics, Xinyang Normal University, Xinyang, China, Communication ASIC Design Centre, Tongji University, Shanghai, China
  • Ke Gong College of Physics & Electronics, Xinyang Normal University, Xinyang, China
  • You-chao Tu College of Physics & Electronics, Xinyang Normal University, Xinyang, China
  • Xiao-li Zhang College of Physics & Electronics, Xinyang Normal University, Xinyang, China
  • Xin-wu Chen College of Physics & Electronics, Xinyang Normal University, Xinyang, China

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