원문정보
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초록
영어
H. 264 / AVC is a kind of newest video standards, the use of all kinds of complex forecasting mechanism, makes the compression ratio greatly to ascend, which provides a reliable algorithm support for high-definition video real-time transmission. In this paper, in order to balance boundary treatment of data dependency relationship and macro block filtering the speed of contradictions, a kind of H.264 to block filter hardware structure in SMIC0 was proposed. Under the library 0.13μm CMOS, the comprehensive results show that the circuit in the 300 MHZ clock frequency consumption 40000 logic gates, which needs 64 clocks cycle to deal with a 16 x16 macro block.
목차
Abstract
1. Introduction
2. Deblocking Filtering Algorithm
2.1. Algorithm
2.2. The Original Filter Order
3. Hardware Design of Deblocking Filtering
3.1. The Optimized Filtering Order
3.2. A Filter Processing Unit
3.3. Transposition Module
4. Experimental Results and Analysis
5. Conclusion
Acknowledgments
References
1. Introduction
2. Deblocking Filtering Algorithm
2.1. Algorithm
2.2. The Original Filter Order
3. Hardware Design of Deblocking Filtering
3.1. The Optimized Filtering Order
3.2. A Filter Processing Unit
3.3. Transposition Module
4. Experimental Results and Analysis
5. Conclusion
Acknowledgments
References
저자정보
참고문헌
자료제공 : 네이버학술정보