원문정보
초록
영어
This paper presents a VLSI implementation of reduced -complexity and reconfigurable MIMO(Multiple-Input Multiple-Output) signal detector targeting 3GPP-LTE standard. In recent wireless communication system, MIMO technology is considered as the key technique in LTE to meet the target. Maximum Likelihood (ML) detection is the optimal detection algorithm for MIMO systems. FPGA implementation of ML detector becomes infeasible as its complexity grows exponentially with the increase in number of antennas. Therefore, we propose a modified K-best detector algorithm which employs parallel and distributed sorting strategy combined with bitonic sorter that has near-ML detection solution. The design was implemented targeting Xilinx Spartan 6 device and the resource utilization results are presented and the performance comparison with the literature was also done. The total on-chip power estimated is 213mW.
목차
1. Introduction
2. MIMO System Model
2.1. Sphere Decoding Algorithm
3. K-Best Algorithm
4. Real –valued Decomposition
5. Modified K-best Algorithm
6. VLSI Architecture
6.1. Bitonic Sorter
7. Implementation and Results
8. Conclusion
References