원문정보
초록
영어
This paper presents low-power Programmable Gain Amplifier (PGA) with a DC-offset cancellation for a direct conversion receiver (DCR) to reduce chip area, cost and power. In the receiver stage, the direct conversion architecture has simplified scheme as compared to the conventional super-heterodyne architecture because IF stage could be omitted in the direct conversion architecture, and the system can be a single chip. The PGA controls 8-level gains from 4dB to 60dB using the CMOS switches and passive resistors in parallel, and DC-offset circuit is based on a Miller effect technique. It is fabricated using Magnachip/SK Hynix 0.18-μm CMOS 1poly-6metal process. The proposed system showed excellent gain error of less than 0.24dB, very small die area of 0.015mm2 and low power consumption of 1.137mW.
목차
1. Introduction
2. PGA with DC-offset Cancellation Circuit
2.1. PGA Circuit Design
2.2. DC-offset Cancellation Circuit Design
2.3. Proposed PGA with DC-offset Cancellation Circuit
3. Results
4. Conclusions
Acknowledgement
References