earticle

영어

A 10 Gb/s equalizer consisting of analog equalizer and two-tap half-rate decision feedback equalizer (DFE) in 0.18m CMOS has been designer. By employing capacitive degeneration and inductive peaking techniques, the analog equalizer achieves large boosting. The pipelined half-rate architecture is used to improve the transmitted data rate in DFE with a small increase in area. Measurement results show that the distorted signal is well recovered by this equalizer and consumes 27 mW with the supply voltage of 1.8-V. The overall chip area including pads is 0.60.7 mm2.