earticle

영어

This paper presents a comparative research of low-power and high-speed full adder cells which are based on XOR-XNOR algorithm. The adder cells are decomposed into small modules and all of them have an in-depth analysis. Several designs of each of them are implemented, optimized, simulated and analyzed separately. We also design a novel XOR-XNOR module built upon bootstrapped pass transistor logic use silicon on insulator (SOI) process with the characteristics of the full voltage swing at internal nodes and low short-circuit current which helps in reducing the power-delay product (PDP) for high performance applications. Many different full adder cells are constructed with different XOR-XNOR modules. A realistic test environment with buffers and loads are used for simulation. All full adder cells were simulated by HSPICE based on 130 nm CMOS technology at 1.2 V supply voltages. Four sets of frequencies were operated: 25 MHz, 50 MHz, 100 MHz and 200 MHz with 50% duty cycle at four different load capacitances. A comprehensive comparison and analysis are also carried out to test the performance of the adders. Each of these cells shows different performances in terms of power consumption, speed, and PDP. The simulation results of this research are expected to help designers to select the appropriate full adder cell that satisfies their specific applications.