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논문검색

Cordic Iterations based Architecture for Low Power and High Quality DCT

초록

영어

Discrete Cosine Transform (DCT) is widely used in image and video compression standards. This paper presents low-power co-ordinate rotation digital computer (CORDIC) based reconfigurable discrete cosine transform (DCT) architecture. All the computations in DCT are not equally important in generating the frequency domain output. Considering the important difference in the DCT co-efficient the number of CORDIC iterations can be dynamically changed to reduce the power of consumption with improved image quality. The proposed CORDIC based 2D DCT architecture is simulated using Modelsim and the experimental results show that our reconfigurable DCT achieves power savings with improved image quality.

목차

Abstract
 1. Introduction
 2. Related Works
 3. Cordic based DCT Architecture
  A. Cordic Architecture:
  B. Cordic Based DCT Architecture:
 4. Proposed Low Power Cordic based DCT
 5. Reconfigurable Cordic based DCT Architecture
 6. Experimental Results of the Proposed Low Power Cordic based DCT Architecture
 7. Conclusion
 References

저자정보

  • N. Prasannan Assistant Professor, Department of Electronics and Communication Engineering, Selvam College of Technology, India

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