원문정보
초록
영어
Many different factors, such as topology, routing technique, selection function, flow control policy, complexity of router design, contribute to the performance of networks on chip (NoCs). Among these factors, the choice of topology and routing function has a significant effect on the average packet latency and saturation behavior. Torus is popular in many application domains, while the problem of virtual channel misbalance caused by its deadlock avoidance scheme brings lots of performance pathologies. In this paper, we present a novel deadlock avoidance scheme based on draining scheme, and propose a deadlock-free routing scheme for torus networks. We quantify the effects of the proposed routing scheme on the overall network performance by presenting simulation results for 1-D torus and 2-D torus NoCs. Experimental results show that the novel routing algorithm for torus networks could make more efficient use of virtual channel resources, and hence cutting down packet latency and boosting throughput. Note although this paper has considered 1-D and 2-D torus networks in the experimental evaluation, the new scheme is flexible enough to support high-radix torus networks.
목차
1. Introduction
2. Related Work
3. The Proposed Routing Algorithm
3.1 Draining Technique
3.2 Description of the Proposed Routing Algorithm
3.3 Deadlock Freedom Proof of DTDOR
4. Evaluation
4.1 Traffic Pattern and Evaluation Metrics
4.2 Results and Discussion
5. Conclusion
Acknowledgement
References