원문정보
초록
영어
A novel architecture FFT processor which can carry on 1-D FFT algorithm or 2-D FFT algorithm corresponding different size of FFT is proposed in this paper. The architecture is served as a scalable IP Core which is suitable for the heterogeneous multi-core SoC on chip application. The mixed architecture FFT processor achieves balance between high processing speed and resources. Compared with a conventional 1-D FFT processor, this FFT processor is characterized by having smaller resources consumption; compared with a 2-D FFT processor which is mapped onto a long point FFT architecture, it has higher processing speed. It employs the Radix-2 DIT-FFT algorithm and fixed addressing structure. It takes two ways to hide time consumed on data-path, one is read-ahead operation of dual-port RAM to hide the delay introduced by 12-stages pipeline of butterfly-unit and Memory access delay; the other is Ping-Pong operation of 3 groups of RAM to conceal data transmitting time. It also adopt twiddle factor compression algorithm to reduce ROM space. It can carry out 2n (n is from range of 5 to 14) single-precision floating-point FFT/IFFT directly. As a result, we have implemented the mixed architecture FFT processor based on FPGA, and successfully applied it into the heterogeneous multi-core SoC.
목차
1. Introduction
2. One-dimensional FFT processor
2.1 The compression algorithm of twiddle factor
3. Two-dimensional FFT Processor
3.1 The principle of two-dimensional long point FFT algorithm
3.2 The design of two-dimensional FFT processor
3.3 The principle of Read-ahead operation
4. One-dimensional and Two-dimensional Mixed Architecture FFT Processor
4.1. One-dimensional FFT operation mode
4.2. Two-dimensional FFT operation mode
5. Performance comparison of the three FFT processors
6. Summary
Acknowledgments
References