원문정보
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초록
영어
A 1.1 V 81.8 dB delta-sigma analog-to-digital converter (ADC) is presented. The split time integration technique for implementing multi-bit digital-to-analog converter (DAC) without using DEM has been developed and used. In order to reduce power consumption and area, a successive approximation register (SAR) ADC is employed to function as both multi-bit quantizer and summing adder without using an additional amplifier. The proposed delta-sigma modulator operates at a 640 kHz clock rate and dissipates 850 W with a 1.1 V supply. It achieves 81.8 dB dynamic range (DR), 76.8 dB signal-to-noise and distortion ratio (SNDR) over a 5 kHz signal bandwidth. The core area is 235 m2 in a 45-nm CMOS technology.
목차
Abstract
1. Introduction
2. Architecture
3. Circuit Implementation
3.1. Integrator with the proposed multi-bit DAC
3.2. Proposed multi-bit quantizer using SAR ADC
4. Measurement Results
5. Conclusion
Acknowledgements
References
1. Introduction
2. Architecture
3. Circuit Implementation
3.1. Integrator with the proposed multi-bit DAC
3.2. Proposed multi-bit quantizer using SAR ADC
4. Measurement Results
5. Conclusion
Acknowledgements
References
저자정보
참고문헌
자료제공 : 네이버학술정보