원문정보
초록
영어
Systems have recently performed multiple functions through a combination of several IPs. SystemVerilog has useful components for modeling and verification at System-level. The OOP of SysemVerilog supports only single inheritance in a verification environment based on a layered testbench of SystemVerilog. It is restricted to construct environment verification. SystemC is a language for system level design at multiple abstraction levels and supports multiple inheritance. We adopt SystemC to design components of a verification platform which employ multiple inheritance, and combine it with the SystemVerilog-based verification platform using SystemVerilog DPI and the ModelSim macro in this paper. Employing the multiple inheritance of SystemC makes the design of a verification environment simple and easy through code reusability. Another characteristic of OOP with SystemVerilog and SystemC is that it can create a reconfigurable verification platform.
목차
1. Introduction
2. Environment Using System Verilog & System C
2.1. System Verilog-based Layered Test Bench
2.2. Multiple Inheritance using OOP of System C
3. Implement of System-Level Verification Environment
4. Experimental Results
5. Conclusions
References