earticle

영어

A 5.6-Gb/s/channel 4-pulse amplitude modulation (PAM) transceiver is designed for a high-bandwidth chip-to-chip interface in a display application. The asymmetric 4-PAM signaling scheme is proposed to increase the voltage and time margins, and the implemented scheme reduces the reference noise effect in a receiver by 33%. The proposed asymmetric 4-PAM transceiver is implemented by using a 0.13-μm 1-poly 6-metal CMOS process with a 1.2 V supply. The measured rms jitter of the output clock of the phase-locked loop (PLL) is 4.18 ps at the operating frequency of 700 MHz for 5.6-Gb/s/channel with a quad data rate scheme. The measurement results show that the proposed asymmetric 4-PAM signaling increases the voltage margin by 23.5% without reduction in the time margin as compared with conventional 4-PAM signaling when the noise magnitude of the single reference is 65 mV. The active area and power consumption of a 1-channel transceiver including the PLL are 0.294 μm2 and 6 mW/Gb/s, respectively.