원문정보
보안공학연구지원센터(IJSIP)
International Journal of Signal Processing, Image Processing and Pattern Recognition
Vol.5 No.3
2012.09
pp.181-196
피인용수 : 0건 (자료제공 : 네이버학술정보)
초록
영어
An efficient implementation of discrete cosine transform (DCT) computations is presented based on the Ramanujan ordered number DCT (RDCT), a fast multiplierless DCT algorithm. Due to the simple form of the factorized matrices, the derived architecture can be easily constructed from the cascade of only two types of parameterized hardware modules: shifters and adders. The proposed implementations have many features and advantages, including low complexity, high-throughput and regularity. The regularity of RDCT algorithm and careful operation scheduling has resulted in a very efficient implementation of a multiplierless RDCT in Xilinx Spartan3 FPGA in the terms of logic requirements.
목차
Abstract
1. Introduction
2. Ramanujan ordered DCT (RDCT)
2.1 2-D RDCT: [23, 24]
3. DCT Hardware’s Platforms
3.1 FPGA’s
4. Design and Development of Implementation
4.1 Basic Block Diagram
4.2 Implementation Results
5. Conclusions
References
1. Introduction
2. Ramanujan ordered DCT (RDCT)
2.1 2-D RDCT: [23, 24]
3. DCT Hardware’s Platforms
3.1 FPGA’s
4. Design and Development of Implementation
4.1 Basic Block Diagram
4.2 Implementation Results
5. Conclusions
References
저자정보
참고문헌
자료제공 : 네이버학술정보