원문정보
초록
영어
This paper proposes a hardware error checking approach（CCRC）by using redundancy core for multiprocessor system-on-chip (MPSoC) and describes several main error detection methods based on Software-Implemented Hardware Fault Tolerance (SHIF) idea proposed in literatures. The CCRC approach insert some error detection code in high level code, detect the existing of redundancy core in MPSoC, then complete the calculation of detection code in redundancy core. The author compares the CCRC approach with several main error detection methods on error detection capabilities, area, memory and performance overheads in an experiment platform. The result of comparative evaluation shows that the CCRC approach is effective for MPSoC, taking some advantages in versatility and lower cost.
목차
1. Introduction
2. Related works
3. Introduction of Error Detection Approach
3.1 Software
3.2 Ed4I [12]
3.3 Hybrid [14]
3.4 The CCRC approach
4. Experiment Environments for Verification
4.1 Architecture of experiment platform
4.2 Experiment Plan
5. Experiment Result
5.1 Fault Detection Capabilities Analysis
5.2 Overhead analyses
5.3 Comprehensive comparison
6. Conclusions
Acknowledgements
References