원문정보
초록
영어
The current trend in technology has lead to the emergence of complex Systems-on-Chip (SoC). Traditionally, shared busses were used for communication between the different components in an SoC in which a communication link is shared between components in a time-division fashion, resulting in a communication latency. To overcome the limitations of common bus based design we have proposed Network-On-Chip based SoC architecture. The aim of this work is to present a modified architecture of the routing node to achieve higher area and power efficiency using changes at the RTL architecture level. FPGA implementation of 4x4 Router has been performed on Xilinx Spartan-3 FPGA XC3S400. ASIC implementation has been done using Design Compiler and IC compiler of SYNOPSYS with 90 nm SAED technology library. It was found that the proposed router has latency of 4 clock cycles, occupies 0.2 sq. mm of silicon area and operates at 500 Mhz frequency.
목차
1. Introduction
1.1. Motivation for Network-on-chip based System-on-chip Architecture
1.2. Problem Statement
1.3. Proposed Design and Implementation Task
2. Literature Survey
2.1. Motivation for Router Design
2.2. Network -on- Chip
2.3. NoC Topologies
2.4. Switching Policy
3. Introduction to Generic Network on Chip Architecture
3.1. Routing Node
3.2. Input Blocks
4. Routing Node Simulation Results and FPGA Implementation
4.1. Simulation Results of a 4 x 4 Routing Node
4.2. FPGA Implementation of Routing Node
4.3. Testing Scheme for FPGA
4.4. The Hardware Setup to Implement the 4x4 Router
4.5. ASIC Implementation of Routing Node
5. Conclusion and Future Work
References