원문정보
초록
영어
A new architecture for decimating finite impulse response filters is proposed. The architecture is based on using a number of accumulators; each one accumulates a partial sum corresponding to a unique set of D filter coefficients into the filter output, where D is the decimation factor. In the new decimating filter, the accumulated result of an accumulator is passed to another accumulator once for each period of D input samples, except for that of the last accumulator whereby the filter output is obtained. The size of each accumulator can be minimized, depending on the filter coefficients. A demonstrative FPGA implementation shows that this architecture is more favorable than the widely used polyphase architecture, as it requires much less area at similar power consumption.
목차
1. Introduction
2. New Filter Architecture
3. Numerical Results
4. Conclusion
References