earticle

영어

Hardware implementations of finite field arithmetic using normal basis are advantageous due to the fact that the squaring operation can be done at almost no cost. In this paper, a new word-parallel bit-serial finite field multiplier using normal basis is presented. The proposed architecture takes w clock cycles to compute the product bits, where the value for w, 1≤w≤m, can be arbitrarily selected by the designer to set the trade-off between area and speed. It has been shown that the proposed architecture has significantly lower complexity and critical path delay in comparison to the previously proposed architectures.