An FPGA Based High Speed IEEE - 754 Double Precision Floating Point Adder/Subtractor and Multiplier Using Verilog

Purna Ramesh Addanki; Venkata Nagaratna Tilak Alapati; Mallikarjuna Prasad Avana

An FPGA Based High Speed IEEE - 754 Double Precision Floating Point Adder/Subtractor and Multiplier Using Verilog

원문정보

Purna Ramesh Addanki, Venkata Nagaratna Tilak Alapati, Mallikarjuna Prasad Avana

보안공학연구지원센터(IJAST) International Journal of Advanced Science and Technology Vol.52 2013.03 pp.61-74

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초록

영어

Floating Point (FP) addition, subtraction and multiplication are widely used in large set of scientific and signal processing computation. A high speed floating point double precision adder/subtractor and multiplier are implemented on a Virtex-6 FPGA. In addition, the proposed designs are compliant with IEEE-754 format and handles over flow, under flow, rounding and various exception conditions. The adder/subtractor and multiplier designs achieved the operating frequencies of 363.76 MHz and 414.714 MHz with an area of 660 and 648 slices respectively.

Abstract
1. Introduction
2. Implementation of Double Precision Floating Point Adder/Subtractor
  2.1 Algorithm
3. Implementation of Double Precision Floating Point Multiplier
  3.1 Floating Point Multiplication Algorithm
  3.2 Implementation
4. Rounding and Exceptions
5. Results
6. Conclusion
References

키워드

저자정보

Purna Ramesh Addanki Department of ECE, Sri Vasavi Engineering College, Pedatadepalli, Tadepalligudem, India
Venkata Nagaratna Tilak Alapati Professor of ECE, V.R.Siddhartha Engineering College, Kanuru, Vijayawada, India
Mallikarjuna Prasad Avana Professor of ECE, JNTUK, Kakinada, India

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