earticle

영어

Current Floating-point divisor architectures have low frequency, larger area and high latency in nature. With advent of more graphic, scientific and medical applications, floating point dividers have become indispensable and increasingly important. However, most of these modern applications need higher frequency or low latency of operations with minimal area occupancy. In this work, highly optimized pipelined architecture of an IEEE-754 standard double precision floating point divider is designed to achieve high frequency on FPGAs. By using secondary clock to perform mantissa division the overall latency of the divisor is reduced to 30 clock cycles, i.e. 52% less compared to conventional divisors. This design is mapped onto a Virtex-6 FPGA and an operating frequency of 452.69 MHz is achieved. The proposed design also handles all the IEEE specified four rounding modes, overflow, underflow and various exception conditions.