원문정보
초록
영어
The aim of this work is to reduce the burden task on the DSP processor by transferring a parallel computation part on a configurable circuits FPGA, in automatic speech recognition module design, signal pre-processing, feature selection and optimization, models construction and finally classification phase are necessary. LMS filter algorithm that contains more parallelism and more MACs (multiply and Accumulate) operations is implemented on FPGA Virtex 5 by Xilings , MFCCs features extraction and DTW( dynamic time wrapping ) method is used as a classifier. Major contribution of this work are hybrid solution DSP and FPGA in real time speech recognition system design, the optimization of number of MAC-core within the FPGA this result is obtained by sharing MAC resources between two operation phases: computation of output filter and updating LMS filter coefficients. The paper also provides a hardware solution of the filter with detailed description of asynchronous interface of FPGA circuit and TMS320C6713-EMIF component. The results of simulation shows an improvement in time computation and by optimizing the implementation on the FPGA a gain in space consumption is obtained.
목차
1. Introduction
2. Related Works
3. General Presentation of Digital Filters
3.1. Adaptive Filter Applications
3.2. Least Mean Squares (LMS)
4. FPGA Implementation of LMS Core
4.1. LMS Core Details Design
4.2. Hardware Description of the LMS Filter
4.3. The FSM (Finite State Machine) of the Control Path
5. Implementation of the Speech Processing as a Case of Application
5.1. Experimental Results
5.3. Comparative Study with other Commercial Speech Recognition Processors
6. Conclusion
Acknowledgments
References