원문정보
피인용수 : 0건 (자료제공 : 네이버학술정보)
초록
영어
This paper describes how to design a Galois field GF(28)dividing circuit using double subfield transformation[5]. The circuit is much faster and more efficient than the classical GF(28) divider . Multiplier circuit is used mainly for ECC encoding and for the Encripting machine while the Divider is used for ECC decoding and the Decripting machine. The divider in the paper is designed based on the GF(22) inversing circuit and we applied double subfield transformation. We compared the new design with the classical design in both respects, speed and cost so find the new design is much better than the classical design.
목차
Abstract
1. Introduction
2. The New Divider design
3. Analyzing the Subparts of the New GF(28) Divider based on the GF(22) Arithmetic and Logic Operations
4. New Error Correcting Code and Endecripting Processor structure based on GF(22) field ALU
5. Simulation of the New GF(28) Divider using the GF(22) ALU
5.1 Simulation result
5.2 Comparison of GF(24) Inverse logic gate counts between the logic based on GF(22) field logic and the direct logic
6. Conclusion
References
1. Introduction
2. The New Divider design
3. Analyzing the Subparts of the New GF(28) Divider based on the GF(22) Arithmetic and Logic Operations
4. New Error Correcting Code and Endecripting Processor structure based on GF(22) field ALU
5. Simulation of the New GF(28) Divider using the GF(22) ALU
5.1 Simulation result
5.2 Comparison of GF(24) Inverse logic gate counts between the logic based on GF(22) field logic and the direct logic
6. Conclusion
References
저자정보
참고문헌
자료제공 : 네이버학술정보