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영어

This paper proposes the design of 163-bit GF divider based on an Extended binary GCD algorithm. The proposed algorithm is a modified version of the Extended binary GCD algorithm using standard (Polynomial) basis representation. In this paper, we use reduction polynomial f(x)=x163+x7+x6+x3+1 that is recommended in SEC2 (Standards for Efficient Cryptography), where degree m = 163. The proposed 163-bit modular divider is implemented in FPGA using Verilog HDL, and it operates at a clock frequency of 251 MHz on Xilinx-VirtexII FPGA, where selected device is 4vlx25ff668-12. From implementation results, we will show that computation speed of the proposed scheme is significantly improved than the existing two approaches.